3D DRAM: The Memory Scaling Challenge Explained

The semiconductor industry has a pattern. Hit a physical limit. Panic. File patents. Publish roadmaps. Wait. Then, occasionally, actually solve the problem. DRAM is currently somewhere between the patent-filing and roadmap-publishing stages, and the question of what comes next is more genuinely open than the press releases from Samsung and Micron would have you believe.

Jon Y of Asianometry recently put out a detailed breakdown of where true 3D DRAM stands — not HBM, which stacks finished dies like pancakes using packaging tricks, but actual cell-level 3D stacking in the spirit of what transformed NAND flash a decade ago. It's worth taking seriously, because the underlying physics are unforgiving and the industry's preferred solution keeps bumping into them.

Why DRAM Can't Just Keep Shrinking

Start with the basics. A DRAM cell is one transistor and one capacitor. The transistor is the gatekeeper; the capacitor holds the charge that represents your data. The problem is that capacitors don't like being small. Shrink the capacitor and you get less capacitance, which makes it harder to reliably sense whether the charge is there at all, and forces the memory to refresh itself more frequently — which burns power.

As Jon Y puts it: "Making a smaller capacitor means less capacitance, which has trade-offs. Lower capacitance makes it harder to sense how the charge changes the voltage on the bit line... It also shortens the amount of time the capacitor can hold on to the charge, so we must refresh the DRAM cells faster and more frequently. This is a power sock."

The industry has been fighting this physics problem for decades. The 2000s brought 3D capacitor structures — trench capacitors etched down into the substrate, then stacked capacitors built upward on top of their transistors. High-k metal dielectrics helped preserve capacitance at smaller sizes. EUV lithography enabled finer patterning. The next step in cell design, the 4F-squared layout (a 2F-by-2F cell versus the current 6F-squared standard), offers a 33% area reduction but introduces new headaches, particularly the floating body effect — where charge accumulates in the transistor and causes the capacitor to leak information.

Lam Research projects that lateral scaling hits a hard floor around 1,000 square nanometers per bit — roughly 32 by 32 nanometers — and the industry is expected to reach that limit sometime around 2029 or 2030. After that, the playbook runs out.

The NAND Template and Why It Doesn't Transfer Cleanly

3D NAND is the obvious reference point, and for good reason. When planar NAND hit its own scaling wall, manufacturers did something counterintuitive: they stepped back to a larger, more reliable cell design and compensated by stacking hundreds of layers vertically. The economics work because the expensive lithography steps — etch, channel filling — are done once regardless of how many layers you're producing. You get 300-layer NAND stacks without 300x the lithography cost.

Can DRAM borrow this trick? Structurally, not easily. The core obstacle is the capacitor. In conventional DRAM, capacitors are tall and skinny cylinders — modern ones run 1 to 3 micrometers deep while being only 20 to 30 nanometers wide. That geometry is essential for surface area, and surface area is what gives you capacitance. Stack those cells vertically and each layer becomes too thick to build meaningful numbers of them.

The intuitive fix — just tip the capacitors sideways to make horizontal layers — runs into a manufacturing wall. Existing etching and deposition processes are optimized for vertical work, not lateral. Jon Y cites a 2023 blog post by Benjamin Vincent of Lam Research exploring exactly this problem: the sideways cavities are too hard to etch to the required depth and even harder to fill uniformly. The word lines and bit lines routing becomes a nightmare in the dense lateral space.

Vincent's team didn't stop at identifying the problem. Using a process simulator called SEMulator 3D, they redesigned the architecture around short, wide horizontal capacitors — sacrificing length for width to preserve surface area — with gate-all-around transistors for better current control and bit lines relocated to shared trunks at the ends of the structures. The resulting design, as Jon Y describes it, "kind of looks like a strange Lego pine tree." The broader category is called horizontal capacitor or horizontal nanosheet design.

There are two main variants in the field: vertical bit line (where the bit line runs through all layers, with word lines staying horizontal per layer) and vertical word line (the inverse). Industry observers seem to lean toward vertical bit line as the more promising direction, citing smaller footprint and more direct connection to peripheral CMOS circuits — but neither approach is in production yet.

What the Big Players Are Actually Doing

Micron has been filing patents on horizontally oriented DRAM cells for over a decade, which tells you something about how long this has been a known destination without a confirmed road. Their motivation is characteristically cost-focused: 3D stacking would let them achieve higher capacity without proportionally higher spending. Whether they've cracked the manufacturing challenges remains unconfirmed publicly.

Samsung's progress is better documented. According to Tom's Hardware's coverage of IMW 2024, Samsung revealed plans for a 16-layer 3D DRAM stack, with an intermediate "VCT DRAM" architecture serving as a stepping stone. Jon Y's video identifies Samsung's naming evolution for this technology — VS-CAT (Vertically Stacked Cell Array Transistor), later rebranded to VS-DRAM — and notes that wafer bonding would be used to attach the memory cell wafers to the peripheral CMOS support circuitry, since producing the two together on a single wafer presents its own difficulties.

The Nuclear Option: Get Rid of the Capacitor

If the capacitor is the source of all this trouble in 3D DRAM, the most radical response is to eliminate it. This is exactly what a 2020 paper from IMEC researcher Attilio Belmonte proposed.

The design, called the IGZO 2T0C DRAM cell, replaces the classic one-transistor-one-capacitor structure with two thin-film transistors made from indium gallium zinc oxide — IGZO, a material originally developed in Tokyo in 2004 and commercialized by Sharp for display backplanes in the early 2010s. The memory logic is clever: one transistor handles writes, one handles reads. When the write transistor opens, charge flows into the gate of the read transistor, which stores it via parasitic capacitance. Reading the cell means running a small current through the read transistor — the presence or absence of stored charge changes the channel's conductivity, which tells you whether the bit is a one or zero. Notably, the read is non-destructive, unlike conventional DRAM.

What makes IGZO specifically useful is its near-zero leakage when switched off. Silicon transistors are leaky enough that earlier capacitorless DRAM concepts — floating body DRAM, A2 RAM — worked in theory but underperformed in practice. IGZO's leakage is low enough that the stored charge can persist for up to 400 seconds in some cases — roughly 1,000 times longer than standard DRAM retention times. The transistors can also scale down to 14nm without significant retention loss.

The catches are real, though. The 2T0C cell requires more contacts and interconnects than a conventional cell, which makes it physically larger — some papers put the cell size at 9F-squared, which is not compact. The cell surface isn't flat, either: the interconnects create irregular topology that complicates stacking. And reliability is a genuine concern. Jon Y flags positive bias temperature instability (PBTI) as a specific problem — at elevated temperatures and under constant electric fields, electrons get trapped near the transistor's gate oxide, shifting its threshold voltage and degrading read accuracy over time. Stack these cells in a dense 3D structure and you get exactly the elevated temperatures and mechanical stress that make PBTI worse.

IGZO appears on long-range DRAM industry roadmaps, which is meaningful but not conclusive. Roadmaps are where good ideas go to age. Competing approaches, including designs based on thyristors, are also in development. The announce-patent-roadmap-wait cycle is running at full speed across multiple architectures simultaneously, which is exactly what you'd expect when nobody has found the answer yet — and exactly the kind of moment where the winning design is probably still a surprise.

The Harder Constraint

NAND's 3D revolution was clean in retrospect because NAND is bulk storage — you're optimizing for density and cost per bit, full stop. DRAM is working memory. It has to be fast for random access, endure effectively unlimited write cycles without wearing out, and keep leakage low enough to maintain data integrity under demanding conditions. Those requirements don't relax just because you're stacking cells vertically.

As Jon Y notes: "Bringing NAND's scalability trick over to DRAM would be revolutionary, but it won't be easy."

The wall is real. The approaches are serious. The timeline to production is genuinely unclear. Whether you're watching memory stocks, designing AI infrastructure, or just find the physics interesting, this is one of those technology transitions where the outcome isn't predetermined — the industry knows where it needs to go and is still figuring out how to get there before 2029 closes the door on the alternative.

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Mike Sullivan covers the technology industry for BuzzRAG.