Huawei's Chip Folding Strategy: Bold Plan or

Huawei just announced a new semiconductor scaling strategy, and the headlines have been doing what headlines do — treating a roadmap slide like a shipping product. Before we all start updating our geopolitical threat assessments, it's worth spending fifteen minutes with what Huawei actually said, what's genuinely interesting about it, and what gap remains between a presentation and a chip in your pocket.

The strategy is called Tao scaling, and its central insight is legitimate: the semiconductor industry has been optimizing the wrong thing. According to a figure Huawei cited in the presentation — and it's worth flagging this is their own statistic, methodology unspecified — more than 80% of energy in a modern computing system can go toward moving data rather than computing with it. Whether that figure holds across chip types and workloads or represents a specific high-bandwidth scenario, the underlying physics isn't controversial. RC delay — the combined drag of resistance and capacitance across metal interconnects — is a real and growing constraint on performance. Chips have gotten faster at thinking and relatively slower at talking to themselves.

Huawei's proposed fix: fold the chip. Instead of spreading logic horizontally across a flat die, stack it vertically so that signal paths measured in millimeters shrink to signal paths measured in microns. The Anastasi in Tech breakdown puts it plainly: "What once required information to travel millimeters across a chip now might require only a few microns of vertical travel." The geometry is sound. Building upward instead of outward is exactly how the industry has been thinking for years — AMD's 3D V-Cache, TSMC's SoIC, Intel's Foveros — so Huawei isn't conjuring this from nothing. They're proposing to push it further than anyone has gone with logic-on-logic stacking specifically.

The density number they're dangling is 238 million transistors per square millimeter in their dual-layer implementation, which they project reaching by 2026 and which they describe as eventually equivalent to 1.4 nanometer class density by 2031. At first contact, that sounds implausible from a company locked out of ASML's EUV machines. On closer inspection, it's more nuanced than implausible — and more contested than the headlines suggest.

Here's where the smirk earns its keep.

The critical number in Huawei's roadmap isn't 1.4 nanometers. It's 1.5 microns. Specifically, 1.5 micron hybrid bonding pitch — the density of copper-to-copper connections linking stacked dies. This is what makes the whole architecture work. Stack two logic layers with poor interconnect density and you haven't solved the distance problem; you've relocated it. The connection layer becomes the new bottleneck.

The current state of the art sits somewhere in the range of 9 to 10 microns, depending on whose implementation you're measuring. TSMC's SoIC bonding has been reported around 9 microns in some configurations; Intel's Foveros Direct has been cited as low as 10 microns. These figures move as processes mature, so treat the specific numbers as ballpark rather than specification. The point is directional: Huawei is targeting 1.5 microns, which is roughly six times tighter than where the industry's best current production processes sit.

I've watched enough technology roadmaps to know that a 6x improvement target announced in a presentation, without production yield data or a shipping timeline, deserves a specific kind of attention. Not dismissal — the underlying physics don't lie, and the research direction is clearly where the industry is heading anyway. But the distance between "this is where we need to get" and "this is what we're shipping" has historically been where some very confident roadmaps went to die quietly.

Remember Intel's Itanium? The chip that was going to make x86 obsolete, backed by a genuine architectural insight about instruction-level parallelism, announced with the full weight of Intel's credibility behind it? The idea wasn't wrong. The execution timeline and real-world performance gap between the slides and the silicon took roughly a decade to fully reckon with, and by then x86 had adapted around it. Huawei's situation isn't identical, but the pattern — impressive architectural concept, aggressive manufacturing target, geopolitical weight added to make it feel more urgent — is familiar enough to warrant patience before panic.

Assume Huawei closes the bonding pitch gap. Then what?

Physics shows up again, wearing a different hat. Stacking passive memory on top of logic — which the industry already does — is manageable because memory doesn't switch at compute frequencies. Logic does. Stack two active logic dies on top of each other, both switching billions of times per second, and you've concentrated heat in a volume that has no obvious escape route. A data center can deploy liquid cooling. A smartphone cannot.

And the smartphone is exactly where Huawei is starting. The Kirin processor, not a server chip. As the Anastasi in Tech analysis notes: "A data center can use giant heat sinks and liquid cooling infrastructure, but a smartphone has none of that. It's very thin and it sits in your hand." Solving heat dissipation in a logic-on-logic stack thin enough to fit in a phone is the kind of problem that has a way of humbling timelines. It's not a theoretical obstacle — it's an engineering constraint with no obvious current solution at the scale Huawei is describing.

So you have three hard problems nested inside each other: achieving 1.5 micron hybrid bonding pitch in production (not in a lab, at yield), managing inter-layer heat in a mobile form factor, and doing both at a cost structure that makes the resulting chip commercially viable. Each of those is a serious independent challenge. The 2026 and 2031 targets exist in a world where all three get solved on schedule.

What Tao scaling is, stripped of the framing, is a system-level optimization strategy dressed in transistor-node language. The Anastasi in Tech video is direct about this: "Moore's law gave us more transistors for less money. Tao scaling tries to deliver more performance through packaging, connectivity, and system-level optimization. And that's a perfectly valid strategy, but unlike Moore's law, it makes computing more expensive in exchange for performance."

That's an honest characterization of the trade. Stacking two mature nodes does not produce a new node. 238 million transistors per square millimeter across two layers is not the same thing as 238 million transistors per square millimeter on a single layer at 1.4nm process geometry. The density math works if you're counting total transistors in a footprint. The manufacturing node claim falls apart if you're asking whether Huawei has closed the process gap with TSMC.

IMEC's CFET research — vertically stacked transistors at the device level — represents a longer-horizon path toward true 3D scaling, though CFET timelines from research organizations vary considerably and the jump from lab demonstration to consumer silicon has historically taken longer than projected. The trajectory is real; the schedule is negotiable.

None of this means Huawei's engineering isn't serious. Their multi-patterning work with SMIC on DUV lithography — coaxing 7nm-equivalent geometries from machines not designed for it — demonstrated a capacity for creative constraint engineering that deserves genuine respect. The Tao scaling concept draws on real physics, addresses a real bottleneck, and points in a direction the whole industry is already moving. The engineering talent is there.

What isn't there yet is the 1.5 micron bonding pitch in production, the thermal solution for mobile logic stacking, or a shipping product that demonstrates the architecture at scale.

Huawei knows all of this. That's presumably why the target date is 2031, not 2025. The question worth sitting with isn't whether this is real — the concept is — it's whether the gap between today's 9-ish micron bonding capability and tomorrow's 1.5 micron target closes on Huawei's schedule, or whether it slips the way aggressive semiconductor roadmaps tend to slip when physics and manufacturing yield decide to weigh in.

The next data point won't come from a presentation. It'll come from a teardown.

By Mike Sullivan, Technology Correspondent