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Samsung's zHBM Claims 8x GPU Gains, but the Fine Print Says 4

Samsung's zHBM stacks memory on the GPU via hybrid bonding. We check the 8x claim, the 140C thermal problem, and why nothing ships before 2030.

Mike Sullivan

Written by AI. Mike Sullivan

September 7, 20266 min read
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Stylized GPU topped with glowing Samsung memory stacks, labeled “8X FASTER?” and “ZHBM”

Photo: AI. Dexter Bloomfield

A blurry phone photo of a Samsung slide, taken in a Taipei conference hall, pulled over 600,000 views in about a day. The slide promises up to 8x performance per GPU, triple the energy efficiency, and a 75 to 90 percent cut in thermal resistance. The technology behind those numbers is called zHBM, short for Zero-Interposer High Bandwidth Memory, and per Tom's Hardware, it's one of three next-gen memory concepts Samsung has built around advanced wafer bonding.

The Catch Sits in a Bracket

Under the big 8 on Samsung's own slide, in small print, is a bracket: four to eight times. The ceiling got printed as the headline. None of this exists as silicon yet. What Samsung has actually shown, as the Cloud Codes breakdown notes, is a display mockup and three slide decks in one month, all describing a design target for after 2029.

That's not lying. That's what pre-silicon roadmaps have looked like since forever. But it helps to know what you're looking at before you repost it.

Why Anyone Cares: The Memory Wall

The problem zHBM aims at has a name and a birthdate. Two computer architects, Wulf and McKee, warned about the memory wall back in 1995: processors got faster quicker than memory got wider, so chips spend more time waiting on data than doing math. Thirty years later, the wall is load-bearing for the AI industry.

Every word a model generates is a memory problem. The model's weights live in HBM, high bandwidth memory, and the GPU pulls them in fresh for nearly every token. Today's HBM4 towers sit beside the GPU on a silicon baseboard called an interposer. Each tower feeds the chip through 248 wires, and Nvidia's next platform rings one GPU with eight towers. Samsung's own deck says the amount a model reads at once grows 30x per year, and the interposer has two hard limits: wires exit only through the tower's edge facing the chip, and every bit crosses millimeters of baseboard, burning power in packing circuits at both ends.

Samsung's memory planning chief Choi Jang-seok frames the goal simply: cut the energy it takes to move a single bit.

The Move: Delete the Street

zHBM throws away the interposer and lands the memory tower directly on top of the compute die. The layers aren't soldered with bumps; they're fused copper pad to copper pad, a technique called hybrid bonding. Where solder bumps fit roughly 1,500 signals per square millimeter, fused copper fits about 14,000. The whole surface becomes the connector, data travels micrometers instead of millimeters, and the packing circuits disappear. Choi calls it a vertical highway.

Samsung's Hot Chips 2026 deck ran the numbers on a 1,200W GPU with four memory stacks on top: 230 percent more bandwidth, 70 percent better power efficiency, about 100 watts handed back to compute. That's an 8.3 percent return on a 1,200W part. Across a 12-GPU deployment, the savings cover a thirteenth GPU's worth of math. Useful. Not eight.

Three Rulers in One Month

Here's where the skeptic in me pulls out a chair. Samsung pitched this three ways in a single month, per the video's tally:

  • Early August, at a memory show in Silicon Valley: 8x, against HBM5, a standard that itself ships around 2028.
  • Late August, at Hot Chips: 230 percent more bandwidth than HBM4E. That's 3.3x.
  • September 1, Taipei: 8x again, now against HBM4E.

Same product, three events, three comparison points. When a company changes its baseline more often than its slide template, the baseline is the message.

The Heat Problem, Stated in Degrees

The reason all of this waits until after 2029 is one word: heat. A DRAM cell is a leaky bucket holding a tiny electric charge, and warmth drains it faster, so memory constantly rewrites every cell just to remember. Past 85 degrees Celsius, the JEDEC rulebook doubles the refresh duty, and every extra refresh is bandwidth you paid for and don't get.

Today a GPU's heat escapes upward through its lid. Stack memory up there and you've built an expensive electric blanket whose exhaust path runs through the one chip that hates being warm. Researchers at imec, the Belgian research lab, modeled four memory towers riding a working GPU with no mitigation: silicon spiked past 140 degrees Celsius, versus 69 for the same design sitting beside the chip, according to imec's study. Cooling both faces of the package brought the stack roughly level with today's layout. Slowing the GPU down also worked, at the cost of 28 percent of the throughput.

Samsung's answer is the 75 to 90 percent thermal resistance reduction claim. Against numbers like imec's, that's the figure to hold them to.

Follow the Market Share

Why is Samsung the loudest voice in the room? Counterpoint Research puts SK hynix at 58 percent of early 2026 HBM revenue, with Samsung at 21. Samsung lost the round that pays today's bills, so it's selling tomorrow's architecture. It costs nothing to announce and resets the race. Samsung's DRAM VP reportedly put a finer point on it at the Silicon Valley show: "Samsung is back."

That said, this is one area where skepticism should be aimed carefully. SK hynix told Korean press, via ETNews, that it plans the same endgame: memory stacked directly on the accelerator. Both roadmaps climb the same staircase, logic process first, then the controller gets absorbed, then the interposer disappears. The giants only argue about the year. The standards body has already raised HBM4's height cap so current solder bumps stay viable, and SK hynix says fused copper isn't ready before HBM5. The direction has industry-wide buy-in; the timeline is a knife fight.

My Marker to Watch

Believe the direction, discount the 8. Both memory giants are designing for it, the standards body is bending around it, and independent labs are already fighting its heat. If you run GPUs, the race that pays your bills through 2030 is HBM4E, not zHBM. The number I'd watch: some GPU maker committing to memory-on-logic silicon by the end of 2027, or the post-2029 date slipping further.

And one question nobody on a keynote stage wants to answer: when memory fuses onto the processor, two industries become one part. So who do you buy your computer from then, the company that made the processor or the one that made the memory?

Mike Sullivan covers the technology industry for BuzzRAG.

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