How One Engineer Created the AM5 Motherboard AMD Won't Build

Wendell from Level1Techs has built something AMD doesn't sell: an AM5 motherboard with enough PCIe lanes to matter. Not through some exotic new chipset design, but by reprogramming a $1,200 LRLink card originally meant for NVMe expansion. The result runs four GPUs on a platform that officially supports maybe two.

This is the kind of project that emerges when component shortages meet business requirements. Small and medium businesses can't always justify $10,000 Threadripper systems, but they need more than consumer hardware delivers. AMD put server-class EPYC CPUs in the AM5 socket and called it a day. The PCIe lane problem? Someone else's concern.

The Lane Math That Doesn't Add Up

AM5 platforms give you 24 PCIe lanes from the CPU. Motherboard designers typically allocate 16 to the primary graphics slot, maybe four to an M.2 drive, and route the rest through a chipset that manages slower peripherals. It's adequate for gaming. It's borderline useless for AI workloads that need multiple GPUs talking to each other at full speed.

"PCIe connectivity is just lanes and lanes are fungible," Wendell explains. "They can be spent on all kinds of different things—GPUs, storage, different kinds of storage, networking, you name it."

The fungibility is real. What's less fungible is the physical limitation of how many lanes a CPU can provide. You can split 16 lanes into eight plus eight, or four groups of four, but you can't conjure additional bandwidth from nowhere. Unless you add a bridge chip that does exactly that.

The Broadcom Solution Nobody Advertises

LRLink sells a PCIe expansion card built around a Broadcom controller. It takes 16 Gen 5 lanes in and provides 32 Gen 5 lanes out. The company markets it for NVMe storage arrays—eight drives at four lanes each. Wendell reprogrammed the Broadcom chip to output different configurations: two 16-lane slots, or four 8-lane slots, depending on the workload.

This isn't new technology. Motherboard manufacturers used similar chipsets on X299 and X99 boards when Intel's lane counts were even more restrictive. They stopped because server chips gained lanes and the bridges got expensive. Now Nvidia has integrated this functionality into ConnectX NICs for AI servers, using PCIe Gen 6 switching fabrics. The technology exists at both ends of the market. It's the middle that got forgotten.

The practical implementation looks like a cryptocurrency mining rig—cables everywhere, GPUs in external breakout boards. "Yeah, it's a little bit mess of wires, I'll give you that," Wendell admits. But mining rigs typically connect each GPU with a single PCIe lane because the work happens independently on each card. This setup needs full-speed GPU-to-GPU communication, which the Broadcom bridge enables by keeping traffic off the CPU entirely.

Performance Numbers That Justify The Cost

Running two AMD Radeon Pro W7900 GPUs (64GB VRAM each) with a Ryzen 9950X3D, Wendell measured 107 tokens per second for AI inference when GPUs connected through the CPU at eight lanes each. With the LRLink bridge allowing full 16-lane GPU-to-GPU communication, that jumped to 125 tokens per second—a 17% improvement. For training and fine-tuning workloads, the gain reaches 20%.

"Is that much of a speed bump worth $1,000?" he asks. "It depends on what you're doing. For some people, it definitely would be."

The calculus changes with higher-end hardware. RTX 6000 cards, which draw 600 watts each and carry more memory, see even larger performance improvements because they're not bottlenecked by the bridge—they're freed from CPU-mediated communication that was always going to be slower than direct GPU connections.

There's an irony here. The CPU in modern AI servers is often the slowest component. Even $10,000 CPUs can't keep up with GPU-to-GPU transfer requirements. "PCIe Gen 6 is needed for full bandwidth," Wendell notes. The CPUs don't support Gen 6 yet. The GPUs are ready. The solution is to route around the CPU whenever possible, which is precisely what this Broadcom bridge accomplishes.

What AMD Could Build But Hasn't

Wendell's vision for an ideal AM5 motherboard—or its AM6 successor—centers on lane allocation that reflects actual workloads. Use two PCIe Gen 6 lanes for all rear I/O: USB, Thunderbolt 5, 10-gigabit Ethernet. That's equivalent bandwidth to four Gen 5 lanes, but concentrated where it matters. Route the remaining lanes to expansion slots with meaningful width: four 8-lane slots and a couple of 4-lane M.2 connections.

Will AMD build this? Unlikely. The market for 4-GPU AM5 workstations is small. The people who need this configuration either step up to Threadripper or find workarounds like Wendell's. But the component shortages he mentions aren't theoretical. When you can't get Threadripper boards and your business depends on running AI inference at scale, a $1,200 bridge card starts looking reasonable.

The larger question is whether this remains a niche solution or signals something broader about how hardware develops. Nvidia moved PCIe switching into network cards because they could, and because server buyers will pay for integration. Consumer hardware moves slower, constrained by what the mass market will tolerate in price and complexity. The gap between what's technically possible and what's commercially available keeps widening.

For now, the forbidden motherboard exists as a pile of cables and reprogrammed firmware. It works because PCIe lanes really are fungible, and because someone cared enough to make it work. That's been true of interesting hardware for fifty years.

—Bob Reynolds, Senior Technology Correspondent