AI Chip Supply Chain: A Complete Course Breakdown

Kian, the instructor behind freeCodeCamp's new 2h37m semiconductor supply chain course, drops the reticle limit almost casually: Nvidia's GB300 GPU contains two dies instead of one because the chip they wanted to build is physically too large for a single exposure through the lithography lens. The lens has a maximum size. Nvidia hit it. So they made two chips and glued them together with a 10 TB/s interconnect called NV-HBI.

I love this. All the mystique around cutting-edge GPU design, and one fundamental constraint is: the lens wasn't big enough. Engineers dealt with it by stitching two reticle-sized dies into one logical GPU, something that would have seemed absurd on an earlier generation. The GB300 carries 208 billion transistors across those two dies, 160 streaming multiprocessors per GPU, 20,480 CUDA arithmetic lanes, and eight stacks of HBM3E memory per GPU delivering 288 GB at up to 8 TB/s. A 72-GPU NVL72 rack runs those numbers times 72. Kian puts the estimated cost of one such rack at $4 million and 135 kilowatts of power draw.

The course uses that single GB300 as a thread running through six stages: semiconductor physics, chip design and EDA, foundry manufacturing, memory, advanced packaging, and data center integration. Kian's stated motivation is direct: "You can export your thinking but you can't export your understanding," he says, quoting Andrej Karpathy. His point is that AI knowledge is being concentrated in a small group of people who understand the hardware, and that concentration has consequences for everyone else making decisions about AI infrastructure.

From transistors to the physics of not melting

The physics section covers ground that most explainers skip. Kian walks through why a GB300 GPU runs at 1.7 GHz while CPUs can hit 5 GHz, and why that gap doesn't mean CPUs are faster for AI. Power scales roughly cubically with clock frequency. Running 20,000 cores at 5 GHz would require so much power the chip would fail, and even if it survived, memory bandwidth can't feed data to cores that fast. The cores would spend most of their time idle. The GPU trades per-core speed for massive parallelism and a clock rate the memory system can actually keep up with.

The transistor evolution section explains how the industry responded when shrinking flat (planar) transistors stopped working: quantum tunneling started leaking current through gates that were physically too small to block it. FinFETs, introduced by Intel at 22nm in 2011, raised the channel into a vertical fin so the gate could wrap around three sides. Gate-all-around (GAA) transistors, introduced in Samsung's 3nm process in 2022, wrap the gate around every side of stacked nanosheets. Kian notes that Samsung's initial GAA yields were, per his course figures, in the 50-60% range, below the 70-80% range he describes as commercially comfortable. Qualcomm declined to use the node. Samsung ended up consuming it internally for its own devices until yields improved. TSMC, despite being behind Samsung on GAA announcements, waited until it could do high-volume manufacturing reliably, and Kian says that happened in Q4 2025.

This is the course's recurring argument: being first on a feature announcement and being able to produce chips at scale and profit are different things. TSMC has dominated by optimizing for the second.

The choke points

Kian structures the supply chain around choke points, single places where the entire industry could seize up. The first is EDA software: Synopsys and Cadence together hold roughly 75% of the electronic system design market (along with Siemens EDA at 13%, per the course). These are the tools that convert chip specifications into manufacturable layouts. Without them, chip designers can't produce the files that go to fabs. Kian cites the US restricting EDA sales to China in May 2025, then lifting the restriction six weeks later after China responded with export controls on gallium and germanium. A policy lever, pulled, then quickly unpulled.

The second choke point is leading-edge foundry capacity. TSMC controls roughly 90% of sub-7nm foundry output for logic chips, and Kian puts TSMC's global foundry market share at 72.3% as of Q1 2026, with Samsung Foundry at 6.5% in the same period, citing course data. TSMC's annual capex for 2026, per Kian's figures, sits between $52 and $56 billion, with a daily spend around $150 million. For context, Kian notes that TSMC's market cap has grown to roughly double Taiwan's entire GDP.

Kian cites $800 billion as 2026 industry-wide AI infrastructure capex, upgraded from earlier projections of $600 billion, with projections toward $1 trillion in 2027. These figures come from Kian's course rather than a named analyst report, so treat them as directional. But even if the real number is half that, the implication is the same: HBM production, advanced packaging capacity, and foundry wafer slots are all being demanded faster than supply chains built to serve a smaller AI market can accommodate.

Kian mentions that Nvidia is reportedly considering reducing the HBM allocation per chip for the upcoming Vera Rubin generation because shortages are constraining how many chips Nvidia can actually ship. HBM is made by SK Hynix, Samsung, and Micron, and the manufacturing process is slow and complex: 12 layers of memory stacked vertically with through-silicon vias (TSVs) punching data connections between layers. Those vias take up space that can't store bits, so 3D-stacked HBM is actually less memory-dense than 2D DRAM per layer, accepted as a trade-off for total capacity. When the entire AI industry is scaling at the rate Kian describes, the three companies that make this component become a constraint on how fast AI infrastructure can grow. The GPU era's pressures look different once you understand what's physically bottlenecking each generation.

What Nvidia's moat actually looks like

Kian reports Nvidia's projected 2026 revenue at $215.9 billion with a reported (though not confirmed) gross margin of 71.1% across the whole company. He puts Nvidia's share of AI accelerator revenue at 90% of the total market, per Q2 2026 industry estimates. The margins on AI accelerators specifically are higher than the company average.

CUDA explains a lot of this. Kian describes it as "a software platform with more than 6 million developers," built since 2006, with tuned libraries for every AI workload. A competitor chip has to support all the code written for CUDA to get adoption, which means competing with 18 years of accumulated tooling, not just competing with the hardware itself. This is the moat that the hardware architecture alone can't explain.

The EDA section adds another layer. Developing a new 2nm chip from scratch costs around $725 million by IBS estimates Kian cites, including $314 million in software development and $154 million for verification alone. That's a greenfield estimate assuming no reusable IP, but the point stands: you need a billion dollars before you've made a single production chip, which is why startups like Etched are raising that kind of capital and still targeting 4nm processes where costs are more manageable.

What the course does and doesn't settle

The course covers geopolitics and policy risk in its final section, including US-China export controls, China's domestic fab efforts through SMIC, Taiwan conflict scenarios, and what Kian calls "diverging AI hardware stacks" as the two ecosystems increasingly can't share components or tooling. The course material here is more framework than resolution, which is the right call: nobody knows how these scenarios play out.

Kian flags Japan's critical role in semiconductor materials, though I'd note he presents the specifics as course framing rather than citing a published report, so I'm not going to repeat precise percentages that could mislead. The general picture is consistent with public reporting: specific processing chemicals for photolithography are heavily concentrated in Japanese suppliers, and when supply shocks hit (the Ukraine conflict disrupted neon gas, for instance), they propagate through the whole chain.

The slides are on GitHub, speaker notes included, and the course has no prerequisites beyond basic computer literacy. Kian's teaching style is methodical without being slow, and the GB300 as a continuous example gives the abstractions something to land on.

Here's my actual read on the next two years: the supply chain picture Kian maps is one where AI scaling is increasingly constrained by physical manufacturing limits, not algorithmic ones. HBM shortages, advanced packaging bottlenecks, and the 135 kW per rack power ceiling are the binding constraints on how fast the infrastructure can grow. Anyone making decisions about AI infrastructure, from procurement to policy, is making decisions about a physical system with specific chokepoints. Kian's course is probably the clearest publicly available map of where those chokepoints are.

Yuki Okonkwo, AI and Machine Learning Correspondent